Digital Electronics (Neso Academy)

About this course

Neso Academy's complete digital electronics course: number systems, logic gates, Boolean algebra and K-maps, combinational and sequential circuits. Who it's for: electronics, electrical and computer science students and GATE aspirants. These are the free, official videos of the "Digital Electronics" playlist from the Neso Academy YouTube channel (youtube.com/@nesoacademy). All videos belong to Neso Academy; Sikhami is not affiliated with Neso Academy and simply arranges the public playlist into a course, so you can learn one lesson at a time and keep track of your progress.

What you will learn

• Signals, number systems and complements • Logic gates and Boolean algebra • SOP and POS forms and Karnaugh maps • Adders, subtractors, multiplexers and demultiplexers • Latches, flip-flops and edge triggering • Counters, state machines and programmable logic

Course content

1 section · 202 lectures · 29h 39m

1. 1. Digital Electronics

   • What is Signal?8m
   • What is an Analog Signal?9m
   • What is Digital Signal?8m
   • Need of Digital Signals5m
   • Introduction to Digital Electronics6m
   • Switch and Bits Intuition9m
   • Introduction to Boolean Algebra (Part 1)18m
   • Introduction to Boolean Algebra (Part 2)10m
   • Boolean Algebra Examples (Part 1)7m
   • Boolean Algebra Examples (Part 2)5m
   • Redundancy Theorem (Boolean Algebra Trick)7m
   • Sum of Products (Part 1) | SOP Form12m
   • Sum of Products (Part 2) | SOP Form8m
   • Product of Sums (Part 1) | POS Form11m
   • Product of Sums (Part 2) | POS Form5m
   • SOP and POS Form Examples12m
   • Minimal to Canonical Form Conversion (Part 1)8m
   • Minimal to Canonical Form Conversion (Part 2)5m
   • Examples & Tricks (SOP and POS Forms)12m
   • Positive and Negative Logic5m
   • Dual Form10m
   • Self Dual9m
   • Complement Meaning and Examples7m
   • Venn Diagram5m
   • Switching Circuits (Part 1)11m
   • Switching Circuits (Part 2)12m
   • Statement Problems in Boolean Algebra (Part 1)3m
   • Statement Problems in Boolean Algebra (Part 2)6m
   • Introduction to Number Systems9m
   • Binary Number System8m
   • Decimal to Binary Conversion9m
   • Decimal to Octal Conversion4m
   • Decimal to Hexadecimal Conversion6m
   • Binary to Decimal Conversion5m
   • Octal to Decimal Conversion5m
   • Hexadecimal to Decimal Conversion4m
   • Octal to Binary & Binary to Octal Conversion6m
   • Hexadecimal to Binary & Binary to Hexadecimal Conversion6m
   • Hexadecimal to Octal & Octal to Hexadecimal Conversion5m
   • Binary Addition8m
   • Binary Subtraction5m
   • Binary Multiplication8m
   • Binary Division5m
   • Octal Addition6m
   • Octal Subtraction3m
   • Octal Multiplication4m
   • Hexadecimal Addition5m
   • Hexadecimal Subtraction3m
   • Hexadecimal Multiplication6m
   • r's Complement6m
   • (r-1)'s Complement8m
   • 1's and 2's Complement4m
   • Shortcut for 2's Complement3m
   • Data Representation using Signed Magnitude5m
   • Data Representation using 1's Complement3m
   • Data Representation using 2's Complement7m
   • Binary Subtraction using 1's Complement12m
   • Binary Subtraction using 2's Complement13m
   • Classification of Codes8m
   • Binary Coded Decimal (BCD) Code16m
   • BCD Addition13m
   • Shift Add 3 Method | Simple method for Binary to BCD conversion4m
   • 2421 Code8m
   • Excess-3 Code (XS-3 Code)11m
   • Excess-3 Code Addition9m
   • Introduction to Gray Code6m
   • Binary to Gray Code Conversion7m
   • Gray Code to Binary Conversion5m
   • What is Parity?8m
   • Hamming Code | Error Detection12m
   • Hamming Code | Error Correction5m
   • Logic Gates (Part 1)16m
   • Logic Gates (Part 2)14m
   • Logic Gates (Part 3)12m
   • Logic Gates (Part 4)10m
   • Logic Gates (Part 5) | Important!19m
   • Logic Gates (Part 6) | Important!14m
   • NAND Gate as Universal Gate (Part 1)8m
   • NAND Gate as Universal Gate (Part 2)12m
   • NOR Gate as Universal Gate14m
   • Karnaugh Map (K' Map) - Part 125m
   • Karnaugh Map (K' Map) - Part 214m
   • Karnaugh Map (K' Map) - Part 310m
   • K' Map and Implicants9m
   • 4 Variable Karnaugh Map (Part 1)11m
   • 4 Variable Karnaugh Map (Part 2)8m
   • 4 Variable Karnaugh Map (Part 3)5m
   • Don't Care in Karnaugh Map (K' Map)10m
   • Don't Care in K' Map (Response to Doubt)6m
   • K' Map using Max Terms (Part 1)7m
   • K' Map using Max Terms (Part 2)11m
   • 5 variables K' Map10m
   • Quine-McCluskey Minimization Technique (Tabular Method)23m
   • Digital Electronics Previous Year Solution of DRDO & ISRO (Part 2)7m
   • Digital Electronics Previous Year Solution of DRDO & ISRO (Part 3)7m
   • 4-Bit Even Parity Generator10m
   • Seven Segment Display Decoder6m
   • Seven Segment Display Decoder (Part 2)8m
   • Seven Segment Display Decoder (Part 3)7m
   • Comparison between Combinational and Sequential Circuits6m
   • Half Adder5m
   • Full Adder13m
   • Full Adder using Half Adder7m
   • 4 Bit Parallel Adder using Full Adders10m
   • Half Subtractor6m
   • Full Subtractor | Easy Explanation7m
   • Realizing Half Adder using NAND Gates only6m
   • Realizing Half Adder using NOR Gates only5m
   • Realizing Full Adder using NAND Gates only6m
   • Realizing Half Subtractor using NAND Gates only6m
   • Realizing Half Subtractor using NOR Gates only4m
   • Realizing Full Subtractor using NAND Gates only (Part 1)9m
   • Realizing Full Subtractor using NAND Gates only (Part 2)5m
   • 2-Bit Multiplier Using Half Adders9m
   • Carry Lookahead Adder (Part 1) | CLA Generator6m
   • Carry Lookahead Adder (Part 2) | CLA Adder11m
   • BCD Adder | Simple Explanation15m
   • Introduction to Multiplexers | MUX Basic12m
   • 4X1 Multiplexer5m
   • 8X1 Multiplexer5m
   • MUX Tree Basic | 4X1 MUX using 2X1 MUX | Easy Explanation7m
   • Implementing 8X1 MUX using 2X1 MUX5m
   • Implementing 8X1 MUX using 4X1 MUX (Special Case)7m
   • 32X1 MUX using 8X1 MUX14m
   • Implementation of Boolean Function using Multiplexers8m
   • 1-Bit Full Adder using Multiplexer8m
   • Logical Expression from Multiplexer5m
   • Introduction to Demultiplexer | 1:2 DEMUX9m
   • 1:4 Demultiplexer6m
   • Full Subtractor using 1:8 Demultiplexer8m
   • Demultiplexer as Decoder5m
   • 2-Bit Comparator5m
   • Introduction to Encoders and Decoders6m
   • Priority Encoder10m
   • Decimal to BCD Encoder3m
   • Octal to Binary Encoder4m
   • Hexadecimal to Binary Encoder4m
   • Full Adder Implementation using Decoder5m
   • Practice Problems on Combinational Circuits (Part 1)11m
   • Practice Problems on Combinational Circuits (Part 2)9m
   • Practice Problems on Combinational Circuits (Part 3)11m
   • Practice Problems on Combinational Circuits (Part 4)9m
   • Introduction to Sequential Circuits | Important8m
   • SR Latch | NOR and NAND SR Latch16m
   • What is a Clock?5m
   • Triggering Methods in Flip Flops4m
   • How to get Edge Triggering | Simulation using Multisim11m
   • Difference between Latch and Flip Flop5m
   • Introduction to SR Flip Flop8m
   • Truth Table, Characteristic Table and Excitation Table for SR Flip Flop8m
   • Introduction to D flip flop4m
   • Truth Table, Characteristic Table and Excitation Table for D Flip Flop4m
   • Introduction to JK flip flop7m
   • Truth Table, Characteristic Table and Excitation Table for JK flip flop9m
   • Race Around Condition or Racing in JK Flip Flop8m
   • Master Slave JK Flip Flop9m
   • Behaviour of Master Slave D Flip Flop11m
   • Introduction to T flip flop3m
   • Truth Table, Characteristic Table and Excitation Table for T flip flop5m
   • 5 Steps for Flip Flop Conversions | JK to D Flip Flop Conversion6m
   • T Flip Flop to D Flip Flop Conversion4m
   • SR Flip Flop to JK Flip Flop Conversion7m
   • SR Flip Flop to T Flip Flop Conversion6m
   • Preset and Clear Inputs in Flip Flop5m
   • Introduction to State Table, State Diagram & State Equation10m
   • Design Procedure for Clocked Sequential Circuits19m
   • Mealy and Moore State Machines (Part 1)9m
   • Mealy and Moore State Machines (Part 2)4m
   • Analysis of Clocked Sequential Circuits (with D Flip Flop)13m
   • Analysis of Clocked Sequential Circuits (with JK Flip Flop)12m
   • Analysis of Clocked Sequential Circuits (with T Flip Flop)8m
   • Sequence or Pattern Detector9m
   • Sequence Detector (Example)15m
   • State Reduction and Assignment7m
   • ASM Chart6m
   • ASM Chart for Moore State Machine6m
   • Difference between Synchronous and Asynchronous Sequential Circuits2m
   • Introduction to Counters | Important11m
   • Types of Counters | Comparison between Ripple and Synchronous counters7m
   • 3 Bit Asynchronous Up Counter11m
   • 4 Bit Asynchronous Up Counter9m
   • 3 bit & 4 bit Asynchronous Down Counter10m
   • 3 Bit & 4 Bit UP/DOWN Ripple Counter10m
   • Modulus of the Counter & Counting up to Particular Value13m
   • State Diagram of a Counter7m
   • Decade (BCD) Ripple Counter9m
   • How to Design Synchronous Counters | 2-Bit Synchronous Up Counter12m
   • 3-Bit Synchronous Up Counter12m
   • 3-Bit & 4-bit Up/Down Synchronous Counter19m
   • Ring Counter14m
   • Johnson's Counter (Twisted/Switch Tail Ring Counter)7m
   • Introduction to Registers7m
   • Data Formats and Classification of Registers7m
   • Shift Register (SISO Mode)11m
   • Shift Register (SIPO & PIPO Mode)11m
   • Shift Register (PISO Mode)7m
   • Bidirectional Shift Register7m
   • Universal Shift Register15m
   • Practice Problems on Sequential Circuits (Part 2)7m
   • Practice Problems on Sequential Circuits (Part 3)5m
   • Programmable Logic Array (PLA) | Easy Explanation10m
   • Programmable Array Logic (PAL)9m